1. Field of Invention
The present invention relates to semiconductor memories and in particular to arrays of flash memory cells designed to prevent program and erase disturb.
2. Description of Related Art
One of the problems associated with a flash memory is bit line and word line disturbs which are caused by bit line and word line voltages being coupled to the deselected cells as well as the selected cells on the same bit line or word line during erase, program and read operations. The effect of the bit line and word line disturb is to change the threshold voltage of the disturbed cells. This is an accumulative effect that over time will cause a memory error, will shorten the program and erase cycles, and reduce product life.
In U.S. Pat. No. 5,777,924 (Lee et al.) a flash memory circuit erases adjacent row simultaneously and eliminates over erasure and source disturbance problems associated with conventional flash memories. In U.S. Pat. No. 4,999,812 (Amin) an EEPROM device provides increased speed with lower susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming voltage or erase voltage to the path between the sense amplifiers and the memory array.
A split-gate cell is well known in industry today and has a structure equivalent to two transistors in series. One of the two transistors is an enhancement gate transistors and the other is a stacked gate transistor. These two transistors are geometrically joined with the gate of the enhancement transistor being the control gate of the stacked gate transistor. The stacked gate transistor performs like a conventional simple stacked gate cell, where its floating gate is formed by a first layer polysilicon under a control gate made from a second layer polysilicon. The number of electrons stored on the floating gate changes the threshold of the stacked gate transistor which determines the value of the stored data on the floating gate. The enhancement gate of the split gate cell performs as a selector for the stacked gate transistor, and has a positive threshold voltage (approximately 0.7 Volt). This allows the enhancement gate to act as a good selector for accessed cells and a good isolator for deselected cells without consideration of the threshold voltage of the stacked gate transistor.
Bit line and wordline disturb conditions occur in memory arrays that use split gate cells. This can occur during programming and reading when a combination of voltages must be applied to a particular split gate cell but also extend to other cells that are deselected. A disturb condition also occurs during erasure of a column of cells where word lines for the cells in the column are at a high negative potential and extend to other cells in other columns that are deselected and inhibited for erasure. Although a particular operation (read, program or erase) are not carried out in the other cells that are inhibited, the bias on a bit line or a word line extends to the other cells that are inhibited and can reduce the charge on the floating gates of those cells, albeit at a slow rate. The charge on the floating gate of a split gate cell determines the threshold voltage which determines the logical value of tie stored data on the stacked gate portion of the split gate cell. The charge can be reduced over time from repeated disturb operations until the threshold voltage of the stacked gate portion of the cell drops below a point where the stored value is in error.